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1

\FAULT

O

Speaker amplifier fault terminal, which is pulled LOW when an internal fault occurs

2

\SD

I

Places the speaker amplifier in shutdown mode while pulled down.

3

FREQ/SDA

I

Dual function pin that functions as an I2C data input pin in I2C Control Mode or as a Frequency Select terminal when in Hardware Control Mode.

4

PBTL/SCL

I

Dual function pin that functions as an I2C clock input terminal in I2C Control Mode or configures the device to operate in pre-filter Parallel Bridge Tied Load (PBTL) mode when in Hardware Control Mode.

5

DVDD

P

Power supply for the internal digital circuitry

6

GAIN0

I

Adjusts the LSB of the multi-bit gain of the speaker amplifier

7

GAIN1

I

Adjusts the MSB of the multi-bit gain of the speaker amplifier

8

SLLEP/ADR

I

In Hardware Control Mode, places the speaker amplifier in sleep mode. In I²C Control Mode, is used to determine the I2C Address of the device

9

MCLK

I

Master Clock used for internal clock tree, sub-circuit/state machine, and Serial Audio Port clocking

10

SCLK

I

Bit clock for the digital signal that is active on the serial data port's input data line

11

SDIN

I

Data line to the serial data port

12

LRCK

I

Word select clock for the digital signal that is active on the serial port's input data line

13

DGND

G

Ground for digital circuitry (NOTE: This pin should be connected to the system ground)

14

NC

-

Not connected inside the device (all "no connect" pins should be connected to ground for best thermal performance, however they can be used as routing channels if required.)

15

LIM

I

Selects mode of Digital Output Clipper or AGC

16

AVDD

P

Power supply for internal analog circuitry

17

PVDDB

P

Power Supply for internal power circuitry of Channel B

18

PVDDB

P

19

BSB+

BST

Connection point for the OUTB+ bootstrap capacitor, which is used to create a power supply for the high-side gate drive for OUTB+

20

OUTB+

O

Positive pin for differential speaker amplifier output B

21

OUTB-

O

Negative pin for differential speaker amplifier output B

22

BSB-

BST

Connection point for the OUTB- bootstrap capacitor, which is used to create a power supply for the high-side gate drive for OUTB-

23

PGND

G

Ground for power device circuitry (NOTE: This terminal should be

connected to the system ground)

24

BSA-

BST

Connection point for the OUTA- bootstrap capacitor, which is used to create a power supply for the high-side gate drive for OUTA-

25

OUTA-

O

Negative pin for differential speaker amplifier output A

26

OUTA+

O

Positive pin for differential speaker amplifier output A

27

BSA+

BST

Connection point for the OUTA+ bootstrap capacitor, which is used to create a power supply for the high-side gate drive for OUTA

28

PVDDA

P

Power Supply for internal power circuitry of Channel A

29

PVDDA

P

30

PVDDA

P

31

GGND

G

Ground for gate drive circuitry (this terminal should be connected to the system ground)

32

GVDD

O

Voltage regulator derived from PVDD supply (NOTE: This pin is provided as a connection point for filtering capacitors for this supply and must not be used to power any external circuitry)

33

SFT_CLIP

I

Sets the maximum output voltage before clipping (Limiter Level)

34

ANA_REG

P

Voltage regulator derived from AVDD supply (NOTE: This terminal is provided as a connection point for filtering capacitors for this supply and must not be used to power any external circuitry)

35

VCOM

P

Bias voltage for internal PWM conversion block

36

ANA_REF

P

Connection point for internal reference used by ANA_REG and VCOM filter capacitors. And connect to system GND net.

/

EP

G

Provides both electrical and thermal connection from the device to the board. A matching ground pad must be provided on the PCB and the device connected to it via solder. For proper electrical operation, this ground pad must be connected to the system ground.